1. Field of the Invention
The present invention relates to the field of semiconductor assembly techniques, and more specifically, to a method for manufacturing a semiconductor device.
2. Description of the Related Art
As semiconductor assembly techniques have been developed, the critical dimension (CD) of a contact has been shrunk greatly, especially for current logic device technology.
As known by those skilled in the art, there are gate-last approaches and gate-first approaches for field-effect transistor manufacturing processes.
In the gate-last approach, a dielectric layer 707 and a dummy gate are formed on a substrate 709, preferably, a lightly doped region (LDD) implantation is carried out herein and then a spacer 703 is formed. After the formation of a gate structure with the dummy gate as described above, source region and drain region implantations are carried out. A first interlayer dielectric layer 705 is then formed and a chemical-mechanical polishing (CMP) process is performed, so as to substantially expose the upper surface of the dummy gate. The dummy gate is then removed and thereafter, a gate dielectric layer and a metal gate are formed, for example, by depositing gate dielectric (in some certain embodiments, it may be a high-K dielectric) and metal gate materials followed by a CMP process so as to form a gate 701. Re-coating of an interlayer dielectric is performed on the gate; a contact hole is subsequently formed, as shown in FIG. 7.
The gate-first approach is similar to the conventional method of forming poly-silicon gate devices. Dielectric layer 707 and gate 701 are formed on a substrate 709. Preferably, the LDD implantation is carried out herein and then the spacer 703 is formed. After the formation of the gate structure as described above, source region and drain region implantations are carried out. A first interlayer dielectric layer 705 is formed to cover the gate and then a contact hole is formed, as shown in FIG. 7.
Generally, covering the gate with the first interlayer dielectric layer 705 is mainly for facilitating the formation of contact holes 721, 723 to the gate and/or the active area, which contact holes are used for forming contact or wiring).
However, with the shrinkage of contact critical dimension, the manufacturing process encounters some challenges, and the risk of open contacts is increased as well. For example, due to the shrinkage of contact critical dimension, a relatively thick resist may cause the etching of a contact hole (or, an open) stop. Moreover, it is difficult to scale the contact CD down to a desired target value.
Further, for a contact hole shared by a contact to the active area and a contact to the gate, an open circuit problem may be encountered. Due to thick resist or overlying variation, the connection between the active area and the gate may be worsened. Besides, the spacer may be etched, leading to an increase of the leakage from the top of the gate.
In addition, the aspect ratio is high for metal CVD (chemical vapour deposition) processes for the contact formation. Therefore, it is difficult to properly control the resistance of the contact so as to be consistent with the designed or desired resistance. Besides, the interlayer dielectric layer deposition has a small process window, which may result in voids.
Therefore, there exists a need to mitigate or address the above problems. To this end, the inventors herein propose a novel and creative method for manufacturing semiconductor devices, so as to mitigate or eliminate one or more problems existing in the prior art.